The present invention generally relates to the art of electronic filters, and more specifically to a narrow-band filter including a sigma-delta modulator implemented in a programmable logic device.
Narrow-band filters, especially finite impulse response (FIR) filters, are utilized in many applications including narrow-band communication receivers, multi-channel RF surveillance systems, and spectrum management solutions. Representing data within a specified dynamic range is frequently accomplished by quantizing the data using a quantizer operating at the Nyquist rate. Each additional bit of resolution in the quantizer provides an increase in dynamic range of approximately 6 dB. Thus, a signal with 60 dB of dynamic range requires 10 bits, whereas 16 bits can represent data with a dynamic range of 96 dB.
A field programmable gate array (FPGA) is a type of programmable logic device (PLD) including a large number of configurable logic blocks (CLBs) that can be programmed and interconnected to implement a desired functional design. Because of the architecture of the FPGA, many filters, and specifically FIR filters, can be easily implemented. An exemplary treatise on this subject is found in an article entitled, xe2x80x9cFIR Filters with. Field-Programmable Gate Arrays,xe2x80x9d by L. Mintzer, Journal of VLSI Signal Processing, No. 6, pp. 119-127 (1993), incorporated by reference herein. Once the design of the FIR filter has been determined, the configuration for implementation in an FPGA can be computed automatically. An example of a computer-aided design (CAD) system which provides this capability is described in an article entitled, xe2x80x9cAutomatic Implementation of FIR Filters on Field Programmable Gate Arrays,xe2x80x9d by S. Mohanakrishnan et al, IEEE Signal Processing Letters, Vol. 2, No. 3, pp. 51-53, March 1995, also incorporated by reference herein.
While the required dynamic range of a system fixes the number of bits required to represent the data as indicated above, it also affects the expense of subsequent arithmetic operations, in particular multiplications. In any hardware implementation, including FPGA- based DSP processors, there are strong economic imperatives to minimize the number and complexity of the arithmetic components employed in the datapath. Specifically, high precision filters, as expressed by the number of binary bits representing the values of the data samples, require high precision multipliers and other elements that must be implemented in an FPGA. Among the functional logic elements of a FIR filter, the multipliers require the largest utilization of resources in the form of CLBs and associated circuitry.
It is possible to implement a FIR filter using only one multiplier, and schedule the multiplier in a time division multiplexed manner to perform the filter calculation. Although: this reduces the number of CLBs needed, the operational speed of the filter would be severely reduced. In fact, in a real-time application, the operational speed could be so low that the filter would be inoperative for its intended use. A compromise solution is to provide a number of multipliers, and then share the multipliers and other elements that must be implemented in the FPGA.
The constant advance of technology requires filters of ever increasing size, complexity, and speed. Thus, the prior art solution of multiplexing a relatively small number of multipliers and other elements is not sufficient to provide the level of performance required for a high performance FIR filter implemented in an FPGA. Therefore, a need exists for overcoming the limitations of the prior art and fulfilling the desired requirements.
In accordance with the present invention, noise shaping is employed to reduce the precision of the input data samples so that the complexity of the multiply-accumulate units in the filter can be minimized. The net result is reducing the amount of field programmable gate array (FPGA) logic resources required to realize a filter while increasing the size and complexity and/or the operating speed of the filter, all without degradation of signal quality over a specified band of frequencies.
To achieve this result, the present invention implements a narrow-band filter in the FPGA. The narrow-band filter includes an analog-to-digital (A/D) converter, a sigma-delta (xcexa3xcex94) modulator, and a lowpass, bandpass, or highpass finite impulse response (FIR) filter. The A/D converter quantizes an input analog signal with a high degree of precision to produce input data samples. The sigma-delta (xcexa3xcex94) modulator re-quantizes the samples to a substantially lower degree of precision. The re-quantized samples are then passed through the FIR filter that operates at the same degree of precision as the modulator output data. The lower degree of precision reduces the number of resources required to implement the FIR filter in the FPGA.
In one embodiment, the xcexa3xcex94 modulator includes a bandpass predictor filter which has the same center frequency as that of the bandpass FIR filter. In this manner, the xcexa3xcex94 modulator redistributes noise such that it is lowest within the passband of the bandpass FIR filter, thereby preventing the signal integrity from being compromised within the passband.
The narrow band filter design of the present invention can be adapted to incorporate a single or multi-rate decimator configuration.